1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming a three-dimensional (3D) semiconductor device, such as a dielectrically isolated FinFET device or a nanowire device, with a strained channel region.
2. Description of the Related Art
The fabrication of advanced integrated circuits typically involves the formation of a large number of field effect transistors (MOSFETs or FETs). For at least 7 nm technology nodes, a number of device options have been considered for forming transistors, e.g., 3D devices such as FinFET devices with dielectric isolation for improved short channel performance and low leakage currents as well as nanowire devices to further reduce short channel effects, etc. It is also known in the art that the performance of a transistor can be improved if the channel region of the device can be appropriately strained. More particularly, the performance of PFET devices and NFET devices is improved if the channel region of such devices is subjected to a compressive or tensile strain, respectively. Such strain may be applied using source and drain epitaxy materials, such as a SiC stressor material for an NFET device and a SiGe stressor material for a PFET device. In addition, strain may be applied to the channel region via the substrate, e.g., a SiGe channel material can be strained relative to a silicon substrate, and silicon channel material can be strained relative to a SiGe substrate or a SiGe strain relaxed buffer layer or structure. As it relates to the formation of 3D devices, there are several problems associated with various prior art techniques of forming such devices with appropriate dielectric isolation and strained channel regions.
FIGS. 1A-1F reflect a prior art FinFET device 10 with bottom dielectric isolation. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed on top of a semiconductor substrate 12 at an intermediate point during fabrication. FIG. 1B is a cross-sectional view of the channel region of the device 10 taken through one of the fins. In this example, the FinFET device 10 includes a plurality of trenches 14 that define three illustrative fin-type structures 16, a trench isolation material 15, a gate structure 18, a gate insulation material 31, sidewall spacers 20 and a gate cap layer 22. In general, the fin-type structure 16, at this point in the process flow, is comprised of a substrate portion 17, a sacrificial portion 19 and what will become the final fin 21 for the device 10. The final fins 21 have a three-dimensional configuration: a height H, a width W and an axial length L. In this embodiment, the substrate portion 17 is made of the substrate material (such as silicon, silicon germanium or a strain relaxed buffer (SRB) layer), the sacrificial portion 19 may be made of, for example, silicon germanium (if the desired final fin 21 is to be made of silicon), and the final fin 21 that will function as the channel region of the device may be made of a material such as silicon for an NFET device and SiGe for a PFET device. The fin-type structure 16 having the three-part structure depicted in FIG. 1A may be formed using several well-known processing techniques. One such technique involves recessing an initial fin structure (i.e., the substrate portion 17) and thereafter performing two epi deposition processes to form the second and third portions 19 and 21. Alternatively, such a three-part fin-type structure 16 may be formed by performing one or more blanket-epitaxial growth processes to grow the various layers of material corresponding to the sacrificial portion 19 and the final fins 21 on the substrate 12, followed by performing an etching process through a patterned masking layer (not shown) to define the three-part fin-type structure 16 shown in FIG. 1A. As noted above, the portions of the final fins 21 covered by the dummy gate structure 18 are the channel regions of the FinFET device 10. In FIGS. 1A and 1B, the substrate material 12 (the portion 17) may have a different lattice parameter or lattice constant than that of the material of final fins 21. In such a case, the vertical thickness of final fins 21 will be less than a critical thickness of the material of the final fins 21 so as not to cause relaxation of the material of the final fin 21. In other words, the final fins 21 inherit the same lateral lattice parameter as the substrate 12 (i.e., the portion 17) and they are in a strained condition.
As indicated above, the second portion 19 of the overall fin-type structure 16 is sacrificial in nature. One problem encountered in forming such FinFET and nanowire devices is how to support the final fins 21 after the sacrificial material 19 is removed while still maintaining the desired strain on the fins 21. In one technique, the gate structures are used to support the fins 21/maintain strain when the sacrificial portions 19 are removed. FIGS. 1C-1D depict the device 10 after a selective etching process was performed to remove the second portion 19 relative to the first and third portions 17 and 21 of the overall fin-type structure 16 and from underneath the gate structure, thereby leaving a gap 23. After the sacrificial portion 19 is removed, the final fins 21, (that includes the channel region of the device) are supported by the gate structure. As noted above, the support by the gate structure is intended to maintain the strain that was initially generated in the final fins 21 via the substrate portions 17, i.e., the substrate 12.
Using the “gate-support” technique, the gap 23 has to be filled with an insulating material. Accordingly, as shown in FIGS. 1E-1F, a conformal deposition process was performed to fill the gap 23 with additional isolation material 25 (e.g., silicon dioxide). In theory, as shown in FIG. 1F, the gap 23 under the gate structure is completely filled with isolation material 25. However, in practice, such complete filling does not always occur. FIG. 1G depicts a situation where the sacrificial portion 19 was not completely removed from underneath the gate structure of the device. As a result, the channel region of the device will not be fully isolated from the substrate. FIG. 1H depicts a situation wherein, even though the sacrificial portion 19 was completely removed, an illustrative void 27 was created in the isolation material 25 when the gap 23 was filled. This occurs, in part, due to the fact that isolation material 25 has to fill the tunnel-like gap 23 under the gate structure. The presence of such voids 27 is detrimental to the isolation function to be provided by the isolation material 25. FIG. 1J depicts a situation where there may be an undesirable consumption of the final fins 21, especially in the areas laterally outside of the gate structure. That is, during the etching process that is performed to remove the sacrificial portion 19 from under the gate structure, an undesirable amount of the final fins 21 may be consumed. Such problems may especially occur when forming both long-channel and short-channel devices on the same substrate. For example, the duration of the etching process that is performed to remove the sacrificial portion 19 may be relatively long to insure complete removal of the sacrificial portion 19 (the situation depicted in FIG. 1G) on the long-channel devices. However, the short-channel devices are also subjected to this longer-duration etching process, which may result in the unwanted consumption of the final fins 21 on the short-channel devices, as reflected in FIG. 1J.
In another technique, the sacrificial material 19 is removed prior to the formation of the gate structures. Using this technique, isolation materials are used to support the fins 21/maintain strain when the sacrificial portions 19 are removed. Such an “isolation-support” technique is depicted in FIGS. 1K-1O. FIG. 1K is a plan view of the product, and FIGS. 1L-1O are cross-sectional side views taken where indicated in FIG. 1K. As shown, three illustrative overall fin-type structures 16 are formed above the substrate 12 and isolated by forming a recessed layer of insulating material 32 that is surrounded by a thicker layer of insulating material 30. See FIGS. 1L and 1M. FIGS. 1N and 1O depict the product after the sacrificial second portions 19 were removed. Note, in this embodiment, the sacrificial portions 19 of the fin-type structures 16 were removed prior to the formation of any gate structures. Thus, the removal of the sacrificial portions 19 is easier using this technique since the etchant materials do not have to “tunnel under” a gate structure. However, at the completion of this process, the relatively long final fins 21 are only supported at their ends by the thicker insulation material 30, at the locations indicated in the dashed-line regions 31 in FIG. 1N. Using this technique, it is intended that the insulation material 30 maintains the strain on the final fins 21 until such time as gate structures are formed on the relatively long final fins 21.
An additional problem that that may be encountered when forming FinFET devices with dielectric isolation is related to the formation of epitaxial semiconductor materials in recessed source/drain regions of such devices. FIGS. 1P-1S depict cross-sectional views of two illustrative gate structures wherein an etching process has been performed to define a cavity 35 where epi semiconductor material will be grown for the source/drain regions for the transistor devices. For illustration convenience, the drawings only depict the scenario wherein the portions of the final fins 21 in the source/drain regions are recessed. However, in other applications, the portions of the final fins 21 in the source/drain region may not be recessed, and the source/drain epi semiconductor materials (not shown) may be grown on the portions of the final fins 21 in the source/drain regions in the form of a cladding material. FIGS. 1P, 1R and 1T depict what is commonly referred to as a partially isolated device (Partial Dielectric Isolation), while FIGS. 1Q, 1S and 1T depict what is commonly referred to as a fully isolated device (Full Dielectric Isolation). The primary difference between the two configurations is that, in the FDI devices, the isolation material 25 is positioned under the source/drain regions, i.e., under the cavities 35, while the isolation material 25 is not present under the source/drain regions (i.e., under the cavities 35) for the PDI devices. Thus, in the PDI devices, the substrate portion 17 is exposed in the bottom of the cavity 35, whereas the isolation material 25 is exposed in the bottom of the cavity 35 for the FDI devices. Such configurations have implications when the epi semiconductor material is formed in the cavities 35 for the source/drain regions for the devices.
FIGS. 1R and 1S depict the devices at a point in time when the process of growing epitaxial semiconductor material 37 in the cavities 35 has started but are not complete. As shown in FIG. 1R, for the PDI devices wherein the substrate portion 17 is exposed in the cavity 35, the growth of epi semiconductor material 37 proceeds from three directions, i.e., the two side surfaces 21X of the final fins 21 and the upper surface 17Y of the substrate portion 17. In contrast, as shown in FIG. 1S, for the FDI devices wherein the isolation material 25 is exposed in the cavity 35, the growth of the epi semiconductor material 37 proceeds from only two directions, i.e., the two side surfaces 21X of the final fins 21. In either case, there is a dielectric surface and multiple crystalline surfaces exposed in the cavity 35.
FIGS. 1T and 1U depict the devices at a point in time when the process of growing epitaxial semiconductor material 37 in the cavities 35 is complete. Due to the growth originating on multiple crystalline surfaces, simplistically depicted defects 39, such as twin defects and stacking faults, are typically present in the final epi material for the source/drain regions due to the interaction when two or more epi growth fronts merge so as to fill the cavities 35. The presence of such defects 39 may undesirably reduce or eliminate the strain that is intended to be imparted to the channel region by the source/drain epi semiconductor material formed in the cavities 35.
The present disclosure is directed to various methods of forming a three-dimensional semiconductor device, such as a FinFET device or a nanowire device, with dielectric isolation and a strained channel region that may reduce or eliminate one or more of the problems identified above.